The present invention relates to system support storage and a computer system.
High performance server systems are typically architected utilizing at least one 64-bit Central Processing Unit (CPU). Multiple of these CPUs can cooperate in a single server system using Symmetric Multi-Processing (SMP) architectures. Well known representatives of such CPUs are the IBM PowerPC® processor family and the server processors compliant with the so-called x86-64 architecture offered by Intel® and AMD®.
In a server system the CPUs are complemented by a variety of special subsystems implementing special product functionality. The CPUs and these subsystems build up the system topology of a server system. FIG. 1 illustrates a system topology for a server system. A subsystem can itself comprise one or more processors. For example, the subsystems can comprise graphic controllers, user interfaces (keyboard, mouse, etc.), system memories (DDR2 SDRAM, etc.), mass storage controllers (Fibre Channel, SCSI, etc.) and associated mass storage devices (hard disk drives, CD-ROMs, etc.), expansion card/board support systems (Infiniband®, PCI Express, PCI-X, etc.), network adapters (Ethernet, WiFi, etc.), controllers for the attachment of low-speed peripheral devices (USB, FireWire, etc.), digital and analog inputs/outputs (DIO, I2C, etc.), etc.
Especially, for their operation in a server system the system CPUs need special additional components (the processing support “chipset”; e.g. Northbridge, Southbridge, SuperIO etc.). The integrated structure of these special additional components is also called the “processor nest”, and can be considered as a special subsystem of the server system. The subsystems of a server system are most commonly implemented by using dedicated controllers. The CPUs as well as the subsystems typically require excessive power-up routines and initialization procedures before the server system is able to load an Operating System (OS)—finally leading to a server system in operational fashion that can launch and execute various applications.
As a very first action to bring the server system alive, the planar board comprising the processor nest and potential subsystem areas (e.g., add-on cards) will be powered up. This process already may require services following a timely defined sequence of bringing up the respective component voltages to exactly defined specification. In the second step when the power-up was successful, the key server system components need to be reset and initialized. The initialization is covering topics like configuring inputs/outputs, allocation of subsystems, setting and calibrating important bus timings, etc.
When the server system is configured and initialized with the basic setup configuration, the server system may require further support for the OS-boot operation, e.g. setting up pre-conditions prior the operating system execution. All the preceding steps are usually called the power-on phase of the server system.
Once the server system reached its normal execution mode, typically further run-time support functions are required to maintain unconstrained server system functionality. These support functions can cover environmental monitoring and control functions such as power and thermal management or functions for the detection of system malfunctions and their recovery. When the server system provides so-called autonomic computing features, also a reconfiguration of the server system may be demanded in parallel to its normal operation.
Typically, the described run-time support functions are serviced by at least one service or sub-system-controller. In a common Blade server system architecture the Base-Board Management Controller (BMC) fulfills this role. The EMC can be represented by one or multiple controllers comprising 8 or 16-bit embedded processors (Hitachi® H8, Intel® 80186, etc.). Other server systems (IBM pSeries, IBM zSeries, etc.) may even require controllers with 32-bit embedded processors (IBM PowerPC® 440, etc.).
The processor nests as well as each of the described service- and subsystem-controllers require dedicated storages providing the data for system reset, configuration, booting and run-time monitoring and support, hereinafter called system data. Especially, the system data can comprise firmware, computer program code that will be executed by processors contained in the subsystems. The system data also comprises so-called Vital Product Data (VPD). Typical VPD information includes a product model number, a unique serial number, product release level, maintenance level, and other information specific to the hardware type. VPD can also include user-defined information, such as the building and department location of the device. The collection and use of vital product data allows the status of a network or computer system to be understood and service provided more quickly.
The specific system support storages are attached to the respective controllers or subsystems and are usually accessible to them only. The main memory of the server is not used as system support storage. The storage requirements are individually defined by the controllers and do have widely varying characteristics and specific attributes:                High or medium or low frequent random read and write access;        Data retention after power off or when an unplanned power-loss occurs (represented by battery backed up memories);        High speed run-time access for read and write (direct controller control memories);        High reliability (guaranteed backup operations and data update operations).        
In order to achieve the desired basic server system attributes also a high reliability is required for all its components. Therefore the contribution to the overall material cost of a server system cannot be neglected for these many specialized data repositories. One contributor to this fact is the increased complexity of the system designs; e.g. by adding expansive board wiring to system planar boards that are wiring constrained already.
A battery backed up implementation for Non-Volatile RAM (NVRAM; RAM: Random Access Memory) is expensive and requires a dedicated long term maintenance concept. Typically, such NVRAM devices are broken after 5 to 6 years of operation and need a compatible replacement that is unlikely to be found on the market then. And the permanent discharge of the battery requires a frequent operation of the server system in order to ensure that stored data are not lost. A Read-Only Memory (ROM) device on the other hand stores the data permanently, but the data can be read only and not be updated.
Flash memory stores information on a silicon chip in a way that does not need power to maintain the information in the chip. In addition, flash memory offers fast read access times and solid-state shock resistance. Flash memory is available in two forms: NOR and NAND, where the name refers to the type of logic gate used in each storage cell. One limitation of flash memory is that while it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a “block” at a time. Starting with a freshly erased block, any byte within that block can be programmed. However, once a byte has been programmed, it cannot be changed again until the entire block is erased. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer random-access rewrite or erase operations.
All flash architectures today suffer from a phenomenon known as “bit-flipping”. On some occasions (usually rare, yet more common in NAND than in NOR), a bit is either reversed, or is reported reversed.
A further inherent limitation of flash memories is the finite number of erase-write cycles (due to wear on the insulating oxide layer around the charge storage mechanism used to store data). For example, today's NOR memories have a maximum number of erase-write cycles in the range from 100000 up to 1 million. Today's NAND flash devices are up to 5 times cheaper than NOR flash memories of equal capacity, can be written 5 to 10 times faster and has ten times the endurance. Since the block size of a NAND flash device is usually eight times smaller than that of a NOR flash device, each NOR block will be erased relatively more times over a given period of time than each NAND block. This further extends the gap in favor of NAND.
However, NAND flash memories do have certain disadvantages compared to NOR flash memories. NAND flash memories do not allow random access reads and can be accessed in blocks of 512 Byte (called pages) only. Therefore code that is stored in NAND flash cannot be executed directly (XIP: eXecute In-Place), but needs to be copied to different random access storage (e.g., RAM) before starting the execution. For the purpose of executing a boot code this is usually circumvented by providing a very small XIP device containing an initial boot code that copies the code from the NAND flash device to a random access device and executes the copied code from there. However, this is a time consuming task and adds additional costs to the overall server system costs.
Due to random errors generated by physical effects in the geometry of the NAND gate, NAND flash memory is prone to low reliability. Due to yield and cost considerations, NAND flash devices are shipped with bad blocks randomly scattered throughout the media. Therefore NAND flash devices need to be initially scanned for bad blocks that have to be marked as unusable.
Various design options for the use of NAND flash memory are available. It is feasible to manage NAND flash memory by means of software executed on a processor alone. However, this leads to a very low performance, mostly due to the heavy error detection code required for every read/write to the flash memory. Therefore, NAND devices usually have an integrated controller, although it is also possible to use separate controllers instead, that provide error detection and correction capabilities already. The most advanced controllers provide NOR flash-like interfaces and boot capabilities to the NAND flash devices. An example of such a NAND flash device with an intelligent controller is the M-Systems DiskOnChip device family. However, even these flash devices have a read/write performance penalty.
The disadvantages of the NAND flash memories prevented its use as data storage in server system topologies in the past. This prejudice is likely to be dropped in the near future when NAND flash devices with intelligent controllers are more visible on the market and have clearly demonstrated their reliability.
Many of the used system storage devices have a low performance characteristic. This can cause negative aspects such as long power-up phases and decreased system performance during the normal operation of the server system. However, configuration updates in NVRAM during the power-on phase and firmware code updates in flash devices are rather rare events today. The patent application U.S. 2004/0123033 A1 incorporated herein by reference proposes to add a volatile storage (e.g., a cache) to an associated memory array within a semiconductor non-volatile memory as a way to mitigate the access penalty that occurs in non-volatile memories such as flash memories.
Magnetoresistive RAM (MRAM) is an NVRAM technology, which has been in development since the 1990s. Continued increases in density of existing memory technologies, notably flash memory and DRAM (Dynamic RAM), have kept MRAM out of the market to date, but proponents believe that the advantages are so overwhelming that MRAM will eventually become widespread. More recently many of the companies working on MRAM have scaled back their efforts, as it appears the system has problems scaling down in size.
Ferroelectric RAM (FRAM or FeRAM) does not yet offer the bit density of DRAM and SRAM, but is non-volatile, is faster than flash memory (write times under 100 nanoseconds, roughly as fast as reading), and has very low power requirements.
Due to their different characteristics, also the effort for programming the various storage devices (NAND flash, NOR flash, ROM, NVRAM) is significant during the development, manufacturing, maintenance, and repair phases for a server system. It likely requires a large set of different tools for each of the different storage devices and also requires providing and maintaining the different storage content in a variety of files.